All-directions embeded module, method for manufacturing the all-directions embeded module, and all-directions packaging structure

ABSTRACT

An all-directions embedded module includes a substrate layer, many first embedded pads, many second embedded pads, and many side wall circuits. The substrate layer comprises a first surface, a second surface opposite to the first surface, and a plurality of side surfaces connected to the first surface and the second surface. The first embedded pads is formed on the first surface. The second embedded pads is formed on the second surface. The side wall circuits embedded in the substrate layer and exposed from the side surfaces. The all-directions embedded module further includes a plurality of first connecting circuits formed on the first surface and a plurality of second connecting circuits formed on the second surface. The first embedded pads is connected to the side wall circuits by the first connecting circuits. The second embedded pads is connected to the side wall circuits by the second connecting circuits.

FIELD

The present disclosure relates to an all-directions embedded module, amethod for manufacturing the all-directions embedded module, and anall-directions packaging structure.

BACKGROUND

Electronic devices may have circuit boards. When the electronic devicebecomes lighter and thinner, passive components may be embedded in thecircuit boards to save space. The embedded passive component includes aninductor component, a capacitor component, a resistor component, or thelike. A method for embedding the embedded passive components in thecircuit boards may be: placing the passive components horizontally incavities, and then adding more layers. The embedded passive componentscannot achieve an all-directions conduction in a packaging structure,which will limit package flexibility and paths of a signal transmission,and will increase packaging processes of manufacturing a packagingstructure.

Therefore, there is room for improvement in the art.

BRIEF DESCRIPTION OF THE DRAWINGS

Implementations of the present disclosure will now be described, by wayof embodiments, with reference to the attached figures.

FIG. 1 is a flowchart of a method for manufacturing an all-directionspackaging structure in accordance with an embodiment.

FIG. 2 is a plan view of an exemplary embodiment of an all-directionsembedded module according to the present disclosure.

FIG. 3 is a cross-sectional view of the all-directions embedded moduleof FIG. 2 along line II-II.

FIG. 4 is a perspective view of the all-directions embedded module (onlywith side wall circuits and a parts of welding pads) of FIG. 2.

FIG. 5 is a flowchart of a method for manufacturing the all-directionsembedded module of FIG. 4 in accordance with an embodiment.

FIG. 6 is a cross-sectional view of a double-sided copper cladsubstrate.

FIG. 7 is a cross-sectional view showing a first inner circuit layer isformed from a first copper layer of the double-sided copper cladlaminate of FIG. 6, and a second inner circuit layer is formed from asecond copper layer of the double-sided copper clad laminate of FIG. 6.

FIG. 8 is a cross-sectional view showing a component is embedded in asubstrate layer of the copper clad laminate of FIG. 7, a firstsingle-sided copper clad laminate is formed on the inner first circuitlayer of FIG. 7, and a second single-sided copper clad laminate isformed on the second inner circuit layer of FIG. 7.

FIG. 9 is a top view showing a plurality of through grooves, a pluralityof first through holes, a plurality of blind holes, and a plurality ofsecond through holes are defined from a first outer copper layer of thefirst single-sided copper clad laminate to a second outer copper layerof the second single-sided copper clad laminate.

FIG. 10 is a cross-sectional view along line VIII-VIII of FIG. 9.

FIG. 11 is a top view of a plurality of first conductive holes, aplurality of second conductive holes, a plurality of third conductiveholes, and a plurality of fourth conductive holes are formed by platinga copper on inner walls of the plurality of through grooves, theplurality of first through holes, the plurality of blind holes, and theplurality of second through holes; a first outer circuit layer and asecond outer circuit layer are respectively formed from the first outercopper layer and the second outer copper layer.

FIG. 12 is a cross-sectional view along line X-X of FIG. 11.

FIG. 13 is a cross-sectional view of a mainboard.

FIG. 14 is a top view showing a plurality of all-directions embeddedmodules is formed on all-directions embedded modules the mainboard inorder (only with side wall circuits and a parts of welding pads), theplurality of all-directions embedded modules is named a first arraylayer.

FIG. 15 is a cross-sectional view along line XIII-XIII of FIG. 14.

FIG. 16 is a cross-sectional view showing conductive material is filledin first gaps between two of the all-directions embedded modules.

FIG. 17 is a cross-sectional view showing a sealing layer is filled insecond gaps between the all-directions embedded modules and themainboard.

FIG. 18 is a cross-sectional view showing a second array layer is formedon the first array layer, a third array layer is formed on the secondarray layer, and a fourth array layer is formed on the third array layerto form a packaging structure.

FIG. 19 is a perspective view of the packaging structure (only with sidewall circuits and a parts of welding pads).

DETAILED DESCRIPTION OF EMBODIMENTS

It will be appreciated that for simplicity and clarity of illustration,where appropriate, reference numerals have been repeated among thedifferent figures to indicate corresponding or analogous elements. Inaddition, numerous specific details are set forth in order to provide athorough understanding of the embodiments described herein. However, itwill be understood by those of ordinary skill in the art that theembodiments described herein can be practiced without these specificdetails. In other instances, methods, procedures, and components havenot been described in detail so as not to obscure the related relevantfeature being described. Also, the description is not to be consideredas limiting the scope of the embodiments described herein. The drawingsare not necessarily to scale and the proportions of certain parts havebeen exaggerated to better illustrate details and features of thepresent disclosure

Several definitions that apply throughout this disclosure will now bepresented.

The term “comprising,” when utilized, means “including, but notnecessarily limited to”; it specifically indicates open-ended inclusionor membership in the so-described combination, group, series, and thelike.

FIG. 1 illustrates a flow chart of a method for manufacturing anall-directions packaging structure in accordance with an embodiment ofthe present disclosure. The example method is provided by way ofexample, as there are a variety of ways to carry out the method. Themethod described below can be carried out using the configurationsillustrated in FIGS. 2-19, for example, and various elements of thesefigures are referenced in explaining example method. Each block shown inFIG. 1 represents one or more processes, methods, or subroutines,carried out in the example method. Additionally, the illustrated orderof blocks is by example only and the order of the blocks can change. Theexample method can begin at block 300.

At block 300, referring to FIGS. 2-12, an all-directions embedded module10 is provided.

FIGS. 2-4 showing an all-directions embedded module 10, theall-directions embedded module 10 includes a substrate layer 201, atleast one electronic element 17, a first outer circuit layer 30, asecond outer circuit layer 40, and a plurality of side wall circuits 61.

The substrate layer 201 includes a first surface 2011, a second surfaceopposite to the first surface 2012, and a plurality of side surfaces2013 connected to the first surface 2011 and the second surface 2012.The component 17 is embedded in the substrate layer 201. The first outercircuit layer 30 is formed on the first surface 2011. The second outercircuit layer 40 is formed on the second surface 2012. The plurality ofside wall circuits 61 is embedded in the substrate layer 201 and exposedfrom the plurality of side surfaces 2013. The plurality of side wallcircuits 61 surrounds the component 17.

The substrate layer 201 further includes a second dielectric layer 21, afirst dielectric layer 11, and a third dielectric layer 23 successivelystacked together. The component 17 is received in the first dielectriclayer 11. The second dielectric layer 21 and the third dielectric layer23 are respectively formed on two opposite surfaces of the firstdielectric layer 11. The second dielectric layer 21 and the thirddielectric layer 23 cover the component 17. The first dielectric layer11 matches the second dielectric layer 21 and the third dielectric layer23 to embed the component 17 in the substrate layer 201.

The component 17 has a plurality of electrodes 171.

The first outer circuit layer 30 includes a plurality of firstconnecting circuits 31 and a plurality of first embedded pads 32. In atleast one embodiment, the plurality of first embedded pads 32 isconnected to the plurality of side wall circuits 61 by the plurality offirst connecting circuits 31. The plurality of first embedded pads 32 isconnected to the component 17.

The second outer circuit layer 40 includes a plurality of secondconnecting circuits 41 and a plurality of second embedded pads 42. Theplurality of second embedded pads 42 is connected to the plurality ofside wall circuits 61 by the plurality of second connecting circuits 41.

The all-directions embedded module 10 further includes a plurality ofthird conductive holes 53 and a plurality of fourth conductive holes 54.The first outer circuit layer 30 is connected to the second outercircuit layer 40 by the plurality of fourth conductive holes 54. Indetail, the plurality of first connecting circuits 31 is connected tothe plurality of second embedded pads 42 by the plurality of fourthconductive holes 54. The plurality of first embedded pads 32 isconnected to the plurality of electrodes 171 of the component 17 by theplurality of third conductive holes 53.

The all-directions embedded module 10 further includes a first innercircuit layer 14 and a second inner circuit layer 15. The first innercircuit layer 14 and the second inner circuit layer 15 are respectivelyformed on two opposite surfaces of the first dielectric layer 11 andembedded in the second dielectric layer 21 and the third dielectriclayer 23.

FIG. 5 illustrates a flow chart of a method for manufacturing anall-directions embedded module in accordance with an embodiment of thepresent disclosure. The example method is provided by way of example, asthere are a variety of ways to carry out the method. The methoddescribed below can be carried out using the configurations illustratedin FIGS. 2-4, and 6-12, for example, and various elements of thesefigures are referenced in explaining example method. Each block shown inFIG. 5 represents one or more processes, methods, or subroutines,carried out in the example method. Additionally, the illustrated orderof blocks is by example only and the order of the blocks can change. Theexample method can begin at block 301.

At block 301, referring to FIG. 6, a double-sided copper clad laminate101 is provided. The double-sided copper clad laminate 101 includes afirst dielectric layer 11, a first copper layer 12, and a second copperlayer 13. The first copper layer 12 and the second copper layer 13 arerespectively formed on two opposite surfaces of the first dielectriclayer 11.

At block 302, referring to FIG. 7, a first inner circuit layer 14 isformed from a first copper layer 12, and a second inner circuit layer 15is formed from a second copper layer 13, thereby obtaining an innercircuit substrate 102.

In other embodiments, the inner circuit substrate 102 can furtherincludes more substrate layer and more inner circuit layers.

At block 303, referring to FIG. 8, a through groove 16 is defined in thefirst dielectric layer 11, a component 17 is embedded in the throughgroove 16, a first single-sided copper clad laminate 103 and a secondsingle-sided copper clad laminate 104 are formed on two opposite surfaceof the first dielectric layer 11.

The first single-sided copper clad laminate 103 includes a seconddielectric layer 21 formed on the first dielectric layer 11 and a firstouter copper layer 22 formed on the second dielectric layer 21. In atleast one embodiment, the first inner circuit layer 14 is embedded inthe second dielectric layer 21.

The second single-sided copper clad laminate 104 includes a thirddielectric layer 23 formed on the first dielectric layer 11 and a secondouter copper layer 24 formed on the third dielectric layer 23. In atleast one embodiment, the second inner circuit layer 15 is embedded inthe third dielectric layer 23.

The first dielectric layer 11, the second dielectric layer 21, and thethird dielectric layer 23 constitute an substrate layer 201. Thecomponent 17 is embedded in the substrate layer 201.

At block 304, referring to FIGS. 9-10, a plurality of through grooves25, a plurality of first through holes 26, a plurality of blind holes27, and a plurality of second through holes 28 are defined from thefirst outer copper layer 22 to the second outer copper layer 24.

The plurality of through grooves 25, the plurality of first throughholes 26, and the plurality of second through holes 28 are all penetratethrough the first outer copper layer 22, the substrate layer 201, thesecond outer copper layer 24, the first inner circuit layer 14, and thesecond inner circuit layer 15. The plurality of blind holes 27penetrates through the first outer copper layer 22 and the seconddielectric layer 21. The plurality of electrodes 171 of the component 17exposes from the plurality of blind holes 27.

The plurality of through grooves 25 abuts the plurality of side surfaces2013. Each of the plurality of through grooves 25 corresponds to one ofthe plurality of side surfaces 2013.

The plurality of first through holes 26 is connected to one of theplurality of through grooves 25. That is, a plurality of first throughholes 26 is located on one side of one of the plurality of throughgrooves 25. The plurality of through grooves 25 and the plurality offirst through holes 26 surround the component 17. The plurality of firstthrough holes 26 is located between the plurality of through grooves 25and the plurality of blind holes 27. The plurality of second throughholes 28 is located between the plurality of first through holes 26 andthe plurality of blind holes 27.

At block 305, referring to FIGS. 11-12, a plurality of first conductiveholes 51, a plurality of second conductive holes 52, a plurality ofthird conductive holes 53, and a plurality of fourth conductive holes 54are formed by plating a copper in the plurality of through grooves 25,the plurality of first through holes 26, the plurality of blind holes27, and the plurality of second through holes 28. A first outer circuitlayer 30 and a second outer circuit layer 40 are respectively formedfrom the first outer copper layer 22 and the second outer copper layer24.

The component 17 has a plurality of electrodes 171. The first outercircuit layer 30 includes a plurality of first connecting circuits 31and a plurality of first embedded pads 32. In at least one embodiment,the plurality of first embedded pads 32 is connected to the plurality ofsecond conductive holes 52 by the plurality of first connecting circuits31. The plurality of first embedded pads 32 is electrically connected tothe component 17 by the plurality of third conductive holes 53. Indetail, the plurality of first embedded pads 32 is electricallyconnected to the plurality of electrodes 171 of the component 17 by aplurality of third conductive holes 53.

The second outer circuit layer 40 includes a plurality of secondconnecting circuits 41 and a plurality of second embedded pads 42. Theplurality of second embedded pads 42 is electrically connected to theplurality of second conductive holes 52 by the plurality of secondconnecting circuits 41. The plurality of first connecting circuits 31 iselectrically connected to the plurality of second embedded pads 42 bythe plurality of fourth conductive holes 54.

At block 306, referring to FIGS. 2-4, a portion of the coppers in theplurality of first through holes 26 are exposed by cutting from an innerwall of the plurality of first through holes 26 to obtaining anall-directions embedded module 10. The coppers in the plurality of firstthrough holes 26 are named a plurality of side wall circuits 61.

At block 400, referring to FIG. 13, a mainboard 150 is provided.

The mainboard 150 supports and determines a position for theall-directions embedded module 10. In detail, the mainboard 150 includesa main substrate layer 151, a plurality of first main pads 152, and aplurality of second main pads 153. The plurality of first main pads 152and the plurality of second main pads 153 are formed on two oppositesurfaces of the mainboard 150. The plurality of first main pads 152 andthe plurality of second main pads 153 determine positions for theall-directions embedded modules 10.

In other embodiments, the plurality of second main pads 153 can beomitted.

At block 500, referring to FIGS. 14-16, a first array layer 110 isformed on and electrically connected to the mainboard 150. The firstarray layer 110 includes many all-directions embedded modules 10. Theall-directions embedded modules 10 are formed on the mainboard 150 inorder. The plurality of second embedded pads 42 of the all-directionsembedded modules 10 is electrically connected to the plurality of firstmain pads 152 of the mainboard 150. Two of the plurality of side wallcircuits 61 of two adjacent all-directions embedded modules 10 facingeach other are electrically connected to each other.

In detail, two of the plurality of side wall circuits 61 of two adjacentall-directions embedded modules 10 facing each other are electricallyconnected to each other by filling conductive materials 72 into firstgaps 71 between the all-directions embedded modules 10 abutting to eachother. In at least one embodiment, the conductive materials 72 aresolders. In other embodiments, the conductive materials 72 also can beplating copper, conductive paste, or the like.

At block 600, referring to FIG. 17, a sealing layer 160 is provided andfilled in second gaps 73 between the first array layer 110 and themainboard 150. The conductive materials 72 is flow-filled in the secondgaps 73.

At block 700, referring to FIG. 18, a second array layer 120 is formedon the first array layer 110 to form an all-directions embedded modulearray 1001, the sealing layer 160 is filled in third gaps 74 between thesecond array layer 120 and the first array layer 110, thereby obtaininga packaging structure 100.

The second array layer 120 includes many all-directions embedded modules10. The all-directions embedded modules 10 are formed on the secondarray layer 120 in order. The plurality of second embedded pads 42 ofthe all-directions embedded modules 10 in the second array layer 120 iselectrically connected to the plurality of first embedded pads 32 of theall-directions embedded modules 10 in the first array layer 110. Theplurality of side wall circuits 61 of the all-directions embeddedmodules 10 abutting to each other are electrically connected to eachother.

In at least one embodiment, the all-directions embedded module array1001 further incudes a third array layer 130 formed on the second arraylayer 120 and a fourth array layer 140 formed on the third array layer130. The third array layer 130 includes many all-directions embeddedmodules 10. The fourth array layer 140 includes many all-directionsembedded modules 10. The all-directions embedded modules 10 are formedon the third array layer 130 in order and formed on the fourth arraylayer 130 in order. The plurality of second embedded pads 42 of theall-directions embedded modules 10 in the third array layer 130 iselectrically connected to the plurality of first embedded pads 32 of theall-directions embedded modules 10 in the second array layer 120. Theplurality of second embedded pads 42 of the all-directions embeddedmodules 10 in the fourth array layer 140 is electrically connected tothe plurality of first embedded pads 32 of the all-directions embeddedmodules 10 in the third array layer 130. The plurality of side wallcircuits 61 of the all-directions embedded modules 10 abutting to eachother are electrically connected to each other.

In other embodiments, the all-directions embedded module array 1001 canfurther incudes more array layer including many all-directions embeddedmodules 10.

In other embodiments, the all-directions embedded module array 1001 canonly include the first array layer.

Referring to FIG. 19, one or more all-directions embedded modules 10 inthe all-directions embedded module array 1001 may also be replaced by apassive element 80. In detail, one of the first array layer 110, thesecond array layer 120, and the third array layer 130 may also bereplaced by the passive component 80. That is, the first array layer 110and/or the second array layer 120 and/or the third array layer 130 mayfurther include a passive component 80. The passive component 80 iselectrically connected to any one of the first embedded pads 32, thesecond embedded pads 42, and the plurality of side wall circuits 61 ofthe all-directions embedded modules 10.

The all-directions embedded modules 10 in the all-directions embeddedmodule array 1001 may have a different volume.

A number of the all-directions embedded modules 10 in the first arraylayer 110, the second array layer 120, the third array layer 130, andthe fourth array layer 140 may be different.

A number of plurality of first embedded pads 32 and the plurality ofsecond embedded pads 42 may be different.

The packaging structure 100 includes a mainboard 150, an all-directionsembedded module array 1001, and a sealing layer 160. The all-directionsembedded module array 1001 is formed on the mainboard 150. The sealinglayer 160 is filled between the mainboard 150 and the all-directionsembedded module array 1001.

The mainboard 150 supports and determines a position for theall-directions embedded module 10. In detail, the mainboard 150 includesa main substrate layer 151, and a plurality of first main pads 152, anda plurality of second main pads 153. The plurality of first main pads152 and the plurality of second main pads 153 are formed on two oppositesurfaces of the mainboard 150. The plurality of first main pads 152 andthe plurality of second main pads 153 determine positions for theall-directions embedded modules 10.

In other embodiments, the plurality of second main pads 153 can beomitted.

The all-directions embedded module array 1001 includes a first arraylayer 110. The first array layer 110 includes many all-directionsembedded modules 10. The all-directions embedded modules 10 are formedon the mainboard 150 in order.

The all-directions embedded module 10 includes an substrate layer 201,at least one component 17, a first outer circuit layer 30, a secondouter circuit layer 40, and a plurality of side wall circuits 61.

The substrate layer 201 includes a first surface 2011, a second surfaceopposite to the first surface 2012, and a plurality of side surfaces2013 connected to the first surface 2011 and the second surface 2012.The component 17 is embedded in the substrate layer 201. The first outercircuit layer 30 is formed on the first surface 2011. The second outercircuit layer 40 is formed on the second surface 2012. The plurality ofside wall circuits 61 is embedded in the substrate layer 201 and exposedfrom the plurality of side surfaces 2013.

The substrate layer 201 further includes a second dielectric layer 21, afirst dielectric layer 11, and a third dielectric layer 23 successivelystacked together. The component 17 is received in the first dielectriclayer 11. The second dielectric layer 21 and the third dielectric layer23 are respectively formed on two opposite surfaces of the firstdielectric layer 11. The second dielectric layer 21 and the thirddielectric layer 23 cover the component 17. The first dielectric layer11 matches the second dielectric layer 21 and the third dielectric layer23 to embed the component 17 in the substrate layer 201.

The component 17 has a plurality of electrodes 171.

The first outer circuit layer 30 includes a plurality of firstconnecting circuits 31 and a plurality of first embedded pads 32. In atleast one embodiment, the plurality of first embedded pads 32 isconnected to the plurality of side wall circuits 61 by the plurality offirst connecting circuits 31. The plurality of first embedded pads 32 isconnected to the component 17.

The second outer circuit layer 40 includes a plurality of secondconnecting circuits 41 and a plurality of second embedded pads 42. Theplurality of second embedded pads 42 is connected to the plurality ofside wall circuits 61 by the plurality of second connecting circuits 41.

The all-directions embedded module 10 further includes a plurality ofthird conductive holes 53 and a plurality of fourth conductive holes 54.The first outer circuit layer 30 is connected to the second outercircuit layer 40 by the plurality of fourth conductive holes 54. Indetail, the plurality of first connecting circuits 31 is connected tothe plurality of second embedded pads 42 by the plurality of fourthconductive holes 54. The plurality of first embedded pads 32 isconnected to the plurality of electrodes 171 of the component 17 by theplurality of third conductive holes 53.

The all-directions embedded module 10 further includes a first innercircuit layer 14 and a second inner circuit layer 15. The first innercircuit layer 14 and the second inner circuit layer 15 are respectivelyformed on two opposite surfaces of the first dielectric layer 11 andembedded in the second dielectric layer 21 and the third dielectriclayer 23.

The plurality of second embedded pads 42 in the all-directions embeddedmodules 10 is electrically connected to the plurality of first main pads152 in the mainboard 150. Two of the plurality of side wall circuits 61of two adjacent all-directions embedded modules 10 facing each other areelectrically connected to each other.

The sealing layer 160 is filled in second gaps 73 between the firstarray layer 110 and the mainboard 150. The conductive materials 72 isflow-filled in the second gaps 73.

In at least one embodiment, the all-directions embedded module array1001 further includes a second array layer 120 formed on the first arraylayer 110, a third array layer 130 formed on the second array layer 120and a fourth array layer 140 formed on the third array layer 130.

The second array layer 120 includes many all-directions embedded modules10. The all-directions embedded modules 10 are formed on the secondarray layer 120 in order. The plurality of second embedded pads 42 ofthe all-directions embedded modules 10 in the second array layer 120 iselectrically connected to the plurality of first embedded pads 32 of theall-directions embedded modules 10 in the first array layer 110. Two ofthe plurality of side wall circuits 61 of two adjacent all-directionsembedded modules 10 facing each other are electrically connected to eachother.

The third array layer 130 includes many all-directions embedded modules10. The fourth array layer 140 includes many all-directions embeddedmodules 10. The all-directions embedded modules 10 are formed on thethird array layer 130 in order and formed on the fourth array layer 130in order.

The plurality of second embedded pads 42 of the all-directions embeddedmodules 10 in the third array layer 130 is electrically connected to theplurality of first embedded pads 32 of the all-directions embeddedmodules 10 in the second array layer 120. The plurality of secondembedded pads 42 of the all-directions embedded modules 10 in the fourtharray layer 140 is electrically connected to the plurality of firstembedded pads 32 of the all-directions embedded modules 10 in the thirdarray layer 130. Two of the plurality of side wall circuits 61 of twoadjacent all-directions embedded modules 10 facing each other areelectrically connected to each other.

In other embodiments, the all-directions embedded module array 1001 canfurther incudes more array layer including many all-directions embeddedmodules 10.

In other embodiments, the all-directions embedded module array 1001 canonly include the first array layer.

Referring to FIG. 19, one or more all-directions embedded modules 10 inthe all-directions embedded module array 1001 may also be replaced by apassive element 80.

In detail, one of the first array layer 110, the second array layer 120,and the third array layer 130 may also be replaced by the passivecomponent 80. That is, the first array layer 110 and/or the second arraylayer 120 and/or the third array layer 130 may further include at leastone passive component 80. The passive component 80 is electricallyconnected to any one of the first embedded pads 32, the second embeddedpads 42, and the plurality of side wall circuits 61 of theall-directions embedded modules 10.

The all-directions embedded modules 10 in the all-directions embeddedmodule array 1001 may have a different volume.

A number of the all-directions embedded modules 10 in the first arraylayer 110, the second array layer 120, the third array layer 130, andthe fourth array layer 140 may be different.

A number of plurality of first embedded pads 32 and the plurality ofsecond embedded pads 42 may be different.

With the above configuration, the all-directions embedded module 10includes an substrate layer 201, the substrate layer 201 includes afirst surface 2011, a second surface 2012 opposite to the first surface2012, and a plurality of side surfaces 2013 connected to the firstsurface 2011 and the second surface 2012. A plurality of first embeddedpads 32 is formed on the first surface 2011, a plurality of secondembedded pads 42 is formed on the second surface 2012, and a pluralityof side wall circuits 61 is embedded in the substrate layer 201 andexposed from the plurality of side surfaces 2013, thereby theall-directions embedded module 10 can be conducted in all directions.Many of the all-directions embedded modules 10 are arranged and packagedon a mainboard 150 in a modular way, thereby greatly improving signaltransmission paths of the packaging structure 100. The all-directionsembedded modules 10 do not need to be encapsulated in an insulatingsubstrate, so there is no need to form an embedded cavity, so apackaging process can be reduced. A number of the all-directionsembedded modules 10 can be increased in various directions according toactual needs, so that a packaging flexibility of the packaging structure100 can be greatly improved.

The embodiments shown and described above are only examples. Even thoughnumerous characteristics and advantages of the present technology havebeen set forth in the foregoing description, together with details ofthe structure and function of the present disclosure, the disclosure isillustrative only, and changes may be made in the detail, includingmatters of shape, size, and arrangement of the parts within theprinciples of the present disclosure, up to and including the fullextent established by the broad general meaning of the terms used in theclaims. It will therefore be appreciated that the embodiments describedabove may be modified within the scope of the claims.

1. (canceled)
 2. (canceled)
 3. (canceled)
 4. (canceled)
 5. A method formanufacturing an all-directions embedded module, comprising: providingan inner circuit substrate, wherein the inner circuit substratecomprises a first substrate layer; and the first substrate layercomprises a plurality of side surfaces; forming a first single-sidedcopper clad laminate and a second single-sided copper clad laminate ontwo opposite surface of the first substrate layer; wherein the firstsingle-sided copper clad laminate comprises a first outer copper; andthe second single-sided copper clad laminate comprises a second outercopper; defining a plurality of through grooves and a plurality of firstthrough holes from the first outer copper layer to the second outercopper layer; wherein the plurality of through grooves are connectedwith the plurality of first through holes; the plurality of throughgrooves abuts the plurality of side surfaces; plating copper in theplurality of through grooves and the plurality of first through holes;and forming a first outer circuit layer and a second outer circuit layerfrom the first outer copper and the second outer copper; the first outercircuit layer comprises a plurality of first embedded pads; the secondouter circuit layer comprises a plurality of second embedded pads; andexposing a portion of the copper in the plurality of first through holesby cutting from an inner walls of the plurality of through grooves; thecopper exposed in the plurality of first through holes formed aplurality of side wall circuits; the plurality of side wall circuits areelectrically connected to the plurality of first embedded pads and theplurality of second embedded pads.
 6. The method of claim 5, wherein atleast one component is embedded in the first substrate layer; furthercomprises: defining a plurality of blind holes from the first outercopper layer to the second outer copper layer; and plating copper in theplurality of blind holes to form a plurality of third conductive holes;the plurality of first embedded pads are electrically connected to thecomponent.
 7. The method of claim 5, wherein the first outer circuitlayer further comprises a plurality of first connecting circuits, theplurality of first embedded pads are electrically connected to theplurality of side wall circuits by the plurality of first connectingcircuits.
 8. The method of claim 5, wherein the second outer circuitlayer comprises a plurality of second connecting circuits, the pluralityof second embedded pads are electrically connected to the plurality ofside wall circuits by the plurality of second connecting circuits. 9.The method of claim 6, further comprising: defining a plurality ofsecond through holes from the first outer copper layer to the secondouter copper layer; and plating the copper in the plurality of secondthrough holes to form a plurality of fourth conductive holes.
 10. Themethod of claim 9, wherein the plurality of first through holes arelocated between the plurality of through grooves and the plurality ofblind holes.
 11. The method of claim 9, wherein the plurality of secondthrough holes are located between the plurality of first through holesand the plurality of blind holes.
 12. (canceled)
 13. (canceled) 14.(canceled)
 15. (canceled)
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